1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an array substrate of an LCD device and a method of fabricating the same that can prevent disconnection of a top metal line due to a step difference in a bottom metal line under the top metal line and crossing the top metal line.
2. Discussion of the Related Art
Generally, LCD devices include first and second electrode bearing substrates coupled to, and spaced apart from each other by a layer of liquid crystal material. LCD devices exploit anisotropic optical properties of the liquid crystal material and display images. In particular, electric fields generated when a voltage is applied to the electrodes on the substrates can selectively manipulate the light transmittance characteristics of the liquid crystal material.
FIG. 1 is a schematic cross-sectional view of an LCD device according to the related art.
In FIG. 1, an LCD device 11 includes upper and lower substrate 5 and 22 facing and spaced apart from each other and a liquid crystal layer 14 between the upper and lower substrates 5 and 22. Here, the upper and lower substrates 5 and 22 include pixel regions “P.” Specifically, the pixel region “P” of the upper substrate 5 and the pixel region “P” of the lower substrate 22 correspond to each other.
A color filter layer 7 including red (R), green (G) and blue (B) sub-color filters 7a, 7b and 7c is formed on an inner surface of the upper substrate 5. A black matrix 6 is formed on the color filter layer 7. Here, each of the red (R), green (G) and blue (B) sub-color filters 7a, 7b and 7c is disposed in the pixel region “P,” and the black matrix 6 is disposed between the sub-color filters 7a, 7b and 7c in a non-pixel region (not shown). Further, a common electrode 18 is formed on the black matrix 6 and the color filter layer 7.
A gate line 12 is formed on an inner surface of the lower substrate 22. A data line 24 is formed over the gate line 12 and crosses the gate line 12 to define the pixel region “P.” A thin film transistor “T” is connected to the gate line 12 and the data line 24. The thin film transistor “T” is adjacent to the crossing of the gate line 12 and the data line 24. In addition, the thin film transistor “T” includes a gate electrode 30, a semiconductor layer 32, and source and drain electrodes 34 and 36. Further, a pixel electrode 17 is connected to the thin film transistor “T” in the pixel region “P.”
Specifically, the liquid crystal layer 14 is interposed between the common electrode 18 and the pixel electrode 17. Here, the liquid crystal layer 14 is pre-aligned by alignment layers (not shown) between the common electrode 18 and the liquid crystal layer 14 and between the pixel electrode 17 and the liquid crystal layer 14. In addition, the alignment layers are rubbed to help the pre-alignment of the liquid crystal layer 14.
Meanwhile, when voltages are applied to the pixel electrode 17 and the common electrode 18, a vertical electric field between the pixel electrode 17 and the common electrode 18 is generated. Therefore, an image can be displayed by varying the transmittance of light in accordance with the vertical electric field.
During the manufacturing process, there are more defects in the process of forming the array substrate which includes the lower substrate 22, the gate line 12, the data line 24, the thin film transistor “T,” and the pixel electrode 17 than in the process of forming the color filter substrate which includes the upper substrate 5, the color filter layer 7, the black matrix 6 and the common electrode 18.
This is because more photolithography processes are performed to form the array substrate. Accordingly, the number of defects of the array substrate is much higher than that of the color filter substrate. Particularly, a top metal line, such as the data line 24, may be easily disconnected at the crossing of a bottom metal line, such as the gate line 12, and the top metal line due to a step difference in the bottom metal line.
FIG. 2 is a schematic plan view of an array substrate with respect to one pixel region according to the related art.
In FIG. 2, an array substrate “AS” includes a gate line 52 and a data line 62 crossing each other to define a pixel region “P,” a thin film transistor “T” adjacent to the crossing of the gate and data lines 52 and 62, and a pixel electrode 64 connected to the thin film transistor “T” in the pixel region “P.”
Here, the gate line 52 and the data line 62 have a crossing portion “III.” In this crossing portion “III,” the data line 62 over the gate line 52 is frequently disconnected due to the step difference in the gate line 52.
Hereinafter, the disconnection defect at the crossing portion “III” of the gate and data lines 52 and 62 will be explained as follows.
FIG. 3 is an expanded plan view of “III” of FIG. 2. FIG. 4 is a schematic cross-sectional view taken along a line of “IV-IV” of FIG. 3.
In FIGS. 3 and 4, the gate line 52 and the data line 62 cross each other with a gate insulating layer (not shown) therebetween.
Generally, because the gate line 52 has a thickness of about 2,000˜3,000 angstrom (Å), the data line 62 disposed over the gate line 52 has a side step difference in the gate line 52 having the above-noted thickness. More particularly, because the gate insulating layer (not shown) is generally made of a silicon nitride (SiNx) or silicon oxide (SiOx) and has a thickness of about 3,000˜4,000 angstrom (Å), the gate insulating layer cannot offset the step difference in the gate line 52. Therefore, at the crossing portion “III” of the gate line 52 and the data line 62, the data line 62 is formed along the step difference in the gate line 52.
Consequently, because the data line 62 is formed along the side step difference portion “SP” in the gate line 52, the data line 62 is easily disconnected at the side step difference portion “SP” due to the deposition defect or the like. Further, an etchant for etching the data line 62 may pool in a concave portion at the side step difference portion “SP.” Therefore, in the concave portion, the data line 62 may be excessively etched. Accordingly, the data line 62 may be disconnected.
The disconnection defect reduces the productivity and increases the manufacturing cost.